Integrated circuit designers have always sought the ideal semiconductor memory: a device that is randomly accessible, can be written or read very quickly, is non-volatile, but indefinitely alterable, and consumes little power. Emerging variable resistance memories increasingly offer these advantages. Chalcogenide-based memory using conductive metal or metal ions in a chalcogenide backbone is one example of such a memory. One such chalcogenide-based memory device is disclosed in U.S. Pat. No. 6,348,365, assigned to Micron Technology Inc. and incorporated herein by reference. Additionally, Magnetoresistive Random Access Memory (MRAM) technology has been increasingly viewed as offering these advantages. Other types of variable resistance memories include polymer-based memory and phase change chalcogenide-based memory.
A chalcogenide-based memory element, employing metal or metal ions, has a structure including a chalcogenide glass region incorporating a metal (or metal ions) and electrodes on either side of the glass region. Information can be stored as a digital “1” or “0” as stable resistance states. A typical chalcogenide glass used in chalcogenide-based memory devices is GexSe100-x. The chalcogenide glass can also be used in conjunction with layers of Ag and/or Ag2Se. The glass region of a chalcogenide-based memory element can be made less resistive upon application of a threshold write voltage. This less resistive state is maintained in a non- or semi-volatile manner and is reversible by applying a reversed voltage. The resistance state of a chalcogenide-based memory element can be sensed by the application of a sub-threshold voltage through the cell element.
A magnetic memory element has a structure which includes ferromagnetic layers separated by a non-magnetic barrier layer that forms a tunnel junction. An example of an MRAM device is described in U.S. Pat. No. 6,358,756 to Sandhu et al. Information can be stored as a digital “1” or a “0” as directions of magnetization vectors in resistance values which depend on the relative pinned and free ferromagnetic layers. Magnetic vectors in one ferromagnetic layer are magnetically fixed or pinned, while the magnetic vectors of the free ferromagnetic layer are not fixed so that the magnetization direction is free to switch between “parallel” and “antiparallel” states relative to the pinned layer. In response to parallel and antiparallel states, the magnetic memory element represents two different stable resistance states, which are read by the memory circuit as either a “1” or a “0.” Passing a current through the MRAM cell enables detection of the resistance states.
Polymer-based memory, another type of variable resistance memory, utilizes a polymer-based layer having ions dispersed therein or, alternatively, the ions may be in an adjacent layer. The polymer memory element is based on polar conductive polymer molecules. The polymer layer and ions are between two electrodes such that upon application of a voltage or electric field the ions migrate toward the negative electrode, thereby changing the resistivity of the memory cell. This altered resistivity can be sensed as a memory state.
Phase change chalcogenide memory, another type of variable resistance memory, switches resistivity states by undergoing a phase change in response to resistive heating. The two phases corresponding to the two stable resistivity states include a polycrystalline state and an amorphous state. The amorphous state is a higher resistance state. The resistance state can be read as stored data.
Typical resistive memory cell arrays employ access transistors to enable the reading and writing of the memory cells. However, power is wasted when an access transistor is used to change the resistance state of a resistance variable memory cell because the power is directed from the power source to ground. Therefore, the access transistor and memory circuit consumes power. Further, the use of an access transistor makes it difficult to stack the memory cells and attain a high memory cell density. A method and apparatus for accessing a variable resistance memory cell without the use of an access transistor is desirable.